Ibraheem El Sheikha

Education

Bachelor of Applied Science (BASc) in Computer Engineering

Thesis: PiazzaPlus - Enhancing Piazza Search with Semantic Matching (Supervised by Professor Salma Emara).
Honours & Awards:
- Top 30 ECE Student (out of ~450 students, 2025–2026)
- Dean's Honours List (2023, 2024, 2025, 2026)
- J. Edgar McAllister Foundation Undergraduate Summer Research Fellowship (one of two selected across all first, second, and third-year ECE applicants, 2025)
- Faculty of Applied Science and Engineering Scholarship (2023)

Microchip Technology | Toronto, ON | 16-month PEY

Developing and migrating core C++ functionality in the synthesis stage of internal FPGA design flows, moving legacy code paths onto modernized implementations.
Debugging interoperability failures between third-party EDA libraries and internal tooling, tracing root causes through multi-million-line Verilog netlists of hierarchical designs with DSP blocks, inferred memories, and multiple clock domains.
Writing Python netlist post-processing utilities that keep output compatible across stages of the FPGA compilation pipeline.
Building automated Bash and Tcl test infrastructure that validates end-to-end design flows across a suite of benchmark designs.

University of Toronto ECE | Toronto, ON

Selected for the J. Edgar McAllister Undergraduate Summer Research Fellowship, working full-time over the summer and continuing part-time through the following academic year up to the paper's presentation.
Developed the hybrid semantic and keyword retrieval pipeline behind PiazzaPlus, deployed through a custom Flask backend.
Designed and ran the evaluation against Piazza's native search, improving MAP by 102.5%, MRR by 143.5%, and P@3 by 72.4%.
Authored and presented the resulting paper as first author at the ASEE Annual Conference & Exposition, supervised by Professor Salma Emara.

Jitterware Inc. | Remote

Designed and developed a multilayer distortion pedal PCB prototype in KiCAD for an electric guitar, complete with a power supply, gain knob, volume control, and tone control.
Selected components in a BOM and optimized routing for a PCBA cost of under $10 CAD.

Verilog • ModelSim • Computer Architecture

Designing a configurable finite state machine processor that executes Varphi, a Turing machine description language, directly in hardware with no program counter and no ALU.
Built a Harvard-architecture datapath in Verilog: a transition-rule ROM addressed by the current state concatenated with the symbol read from each tape, a latched state register, per-tape STAY/LEFT/RIGHT pointers, and tape memory that resets the head to the centre of the address space to maximize runway in both directions.
Parameterized the design over tape count, state width, and symbol width using generate blocks, so the same RTL elaborates to a single-tape or multi-tape machine. Currently simulating a two-tape configuration in ModelSim.
Wrote per-module and top-level testbenches, plus a Python visualizer that animates tape head movement from simulation logs.

Python • ChromaDB • BM25 • Flask • Large Multimodal Models

A published Chrome extension that adds hybrid semantic and keyword search to Piazza, so students can find relevant past discussions instead of reposting them.
Two-stage retrieval: BM25 narrows the corpus to 100 candidates, then cosine similarity over text-embedding-3-large vectors in ChromaDB reranks them, aggregating per-post scores across chunks.
Captioned post images with a vision model and folded the captions into the indexed text, making diagrams, handwriting, and error screenshots searchable.
Built an incremental indexer that hashes the scraped corpus and embeds only new posts on a five-minute cycle, served to the extension through a Flask API.
Chrome Web Store · GitHub Repo

STM32 • Embedded C • UART / I2C • Python

Built the sweep and ranging subsystem of a team-built perimeter scanner on an STM32F446ZE: a stepper sweeps 360° at 1/8 microstepping and fires an ultrasonic ping every 20 microsteps, giving 4.5° of angular resolution.
Integrated identify-friend-or-foe (IFF) over an IR link, where an ESP32 transmits coded pulse frames and the STM32 counts edges in an external interrupt, debouncing at 8 ms and classifying each frame after a 50 ms quiet gap.
Drove an SSD1306 OLED over I2C for local status and streamed polar contact data over UART at 115200 baud.
Wrote a Matplotlib radar display that plots live contacts with an adjustable range ring, colouring each by its IFF result.
GitHub Repo

Embedded C • RISC-V Assembly • FPGA

Built a two-player Reversi game in embedded C on a RISC-V soft processor, driving a VGA display and a PS/2 mouse entirely through memory-mapped I/O.
Integrated double-buffered rendering: pixels are written straight into the back framebuffer at a computed word offset, then the buffers swap and the VGA status register is polled for vertical sync, holding a tear-free 60 Hz.
Decoded PS/2 mouse packets byte by byte out of the data register's RVALID field, put the mouse into stream mode with the 0xF4 command, and mapped cursor position onto board cells.
Wrote the game logic: legal move validation, directional tile flipping, live score rendering, and win detection.
GitHub Repo

Altium • LTSpice • PyVISA

Led a team of three to design, simulate, and manufacture the receive chain for a flexible radio transceiver.
Designed the analog signal chain (8–16 MHz bandpass filter, ±0.7 V limiter, diode ring quadrature mixer, 96 kHz lowpass filter, 32 dB amplifier), verified it in LTspice against the interface control document, and validated the fabricated multilayer Altium PCB on the bench with PyVISA.

Verilog • ModelSim • Quartus

Implemented a RISC-V-inspired CPU from scratch in Verilog with a teammate: register file, ALU, sign-extension unit, controller FSM, datapath muxing, and a memory controller over a 512x32 RAM.
Designed the VGA display interface and the arbitration that lets the processor and the display adapter share one memory without contention.
Built the ALU to cover addi, add, sub, xor, and, or, sw, lw, beq, and bne, verified against directed testbenches in ModelSim and synthesized in Quartus Prime Lite.
GitHub Repo

Peer-Reviewed Conference Paper • First Author • ASEE Annual Conference & Exposition

First author, co-authored with Professor Salma Emara.
Presented at the ASEE Annual Conference & Exposition in Charlotte, North Carolina, the largest engineering education conference in North America, with over 4,000 participants.
One of a small number of undergraduate presenters on a program dominated by faculty researchers.
Covered the deployment and evaluation of hybrid semantic search in a live undergraduate course.
View Paper

Languages: C++, C, Embedded C, Verilog, Python, Tcl, Bash

Hardware & Embedded: RTL design, logic synthesis, computer architecture, RISC-V, FPGAs, EDA, microcontrollers, STM32, UART, SPI, I2C

Tools: Quartus Prime, ModelSim, OneSpin, Linux, Docker, Git, Jira, Confluence

Systems & Software: Data structures, algorithms, operating systems, socket programming, large language models

Always open to discussing research or engineering opportunities. Email is the best way to reach me.

Email: ibraheem.elsheikha@mail.utoronto.ca

LinkedIn: Ibraheem El Sheikha