Ibraheem El Sheikha

University of Toronto Sept. 2023 - Present

Bachelor of Applied Science (BASc) in Computer Engineering

• Honours & Awards:
  • Top 30 of ~450 third-year ECE students (2025–2026)
  • Dean's Honours List (2023, 2024, 2025, 2026)
  • J. Edgar McAllister Foundation Undergraduate Summer Research Fellowship (one of two selected across all first, second, and third-year ECE applicants, 2025)
  • Faculty of Applied Science and Engineering Scholarship (2023)
• Coursework: Operating Systems (A+), Computer Networks (A+), Embedded Systems (A), Algorithms & Data Structures (A), Programming Fundamentals (A), Computer Organization (A−), Computer Fundamentals (A−)
• Thesis: PiazzaPlus: Enhancing Piazza Search with Semantic Matching (A+)
  • Supervisor: Professor Salma Emara

FPGA Software Engineering Intern May 2026 - Present

Microchip Technology | Toronto, ON | 16-month PEY

• Developing and migrating core C++ functionality in the synthesis stage of internal FPGA design flows, moving legacy code paths onto modernized implementations.
• Debugging interoperability failures between third-party EDA libraries and internal tooling, tracing root causes through multi-million-line Verilog netlists of hierarchical designs with DSP blocks, inferred memories, and multiple clock domains.
• Writing Python netlist post-processing utilities that keep output compatible across stages of the FPGA compilation pipeline.
• Building automated Bash and Tcl test infrastructure that validates end-to-end design flows across a suite of benchmark designs.

Undergraduate Researcher May 2025 - June 2026

University of Toronto ECE | Toronto, ON

• Selected for the J. Edgar McAllister Undergraduate Summer Research Fellowship, working full-time over the summer and continuing part-time through the following academic year up to the paper's presentation.
• Developed the hybrid semantic and keyword retrieval pipeline behind PiazzaPlus, deployed through a custom Flask backend.
• Designed and ran the evaluation against Piazza's native search, improving MAP by 102.5%, MRR by 143.5%, and P@3 by 72.4%.
• Authored and presented the resulting paper as first author at the ASEE Annual Conference & Exposition, supervised by Professor Salma Emara.

PCB Engineering Intern Feb. 2025 - Mar. 2025

Jitterware Inc. | Remote

• Designed and developed a multilayer distortion pedal PCB prototype in KiCAD for an electric guitar, complete with a power supply, gain knob, volume control, and tone control.
• Selected components in a BOM and optimized routing for a PCBA cost of under $10 CAD.

Varphi CPU July 2026 - Present

• Designed a processor that runs Varphi, a Turing machine description language, directly in hardware. Each clock cycle it checks one transition rule against the symbols under every tape head, so a step of the Turing machine can take as few as three cycles.
• Stores each state's rules together in a rule memory, most specific first, and uses the address of a state's first rule as its ID, so a state register does the job of a program counter. Rules store each variable as a reference to the tape it was read from, so no variable file is needed and memory grows only with the number of rules.
• Supports the full language: multiple tapes, 21-bit cells for any Unicode symbol, pattern-matching variables, specificity ordering, and nondeterministic ties resolved uniformly with an LFSR and reservoir sampling. Synthesized for an Intel Cyclone V at 84 MHz using 3% of the chip's logic.
• Mapped the rule and tape memories onto FPGA block RAM and built a memory-mapped host interface that loads programs and tapes, starts, single-steps, or stops a run, and reads back the final state, step count, and space used.
• Built a Python regression that runs every test on the RTL in ModelSim and checks the final tapes, state, step count, and space used against the official interpreter, covering all 15 official example programs. Also wrote a visualizer that replays each step, showing which rules the CPU checked and how many cycles it took.

PiazzaPlus May 2025 - June 2026

• A published Chrome extension that adds hybrid semantic and keyword search to Piazza, so students can find relevant past discussions instead of reposting them.
• Two-stage retrieval: BM25 narrows the corpus to 100 candidates, then cosine similarity over text-embedding-3-large vectors in ChromaDB reranks them, aggregating per-post scores across chunks.
• Captioned post images with a vision model and folded the captions into the indexed text, making diagrams, handwriting, and error screenshots searchable.
• Built an incremental indexer that hashes the scraped corpus and embeds only new posts on a five-minute cycle, served to the extension through a Flask API.
• Chrome Web Store · GitHub Repo

STM32 Perimeter Defense System Mar. 2026 - Apr. 2026

• Built the sweep and ranging subsystem of a team-built perimeter scanner on an STM32F446ZE: a stepper sweeps 360° at 1/8 microstepping and fires an ultrasonic ping every 20 microsteps, giving 4.5° of angular resolution.
• Integrated identify-friend-or-foe (IFF) over an IR link, where an ESP32 transmits coded pulse frames and the STM32 counts edges in an external interrupt, debouncing at 8 ms and classifying each frame after a 50 ms quiet gap.
• Drove an SSD1306 OLED over I2C for local status and streamed polar contact data over UART at 115200 baud.
• Wrote a Matplotlib radar display that plots live contacts with an adjustable range ring, colouring each by its IFF result.
• GitHub Repo

Embedded C Reversi Mar. 2025 - Apr. 2025

• Built a two-player Reversi game in embedded C on a RISC-V soft processor, driving a VGA display and a PS/2 mouse entirely through memory-mapped I/O.
• Integrated double-buffered rendering: pixels are written straight into the back framebuffer at a computed word offset, then the buffers swap and the VGA status register is polled for vertical sync, holding a tear-free 60 Hz.
• Decoded PS/2 mouse packets byte by byte out of the data register's RVALID field, put the mouse into stream mode with the 0xF4 command, and mapped cursor position onto board cells.
• Wrote the game logic: legal move validation, directional tile flipping, live score rendering, and win detection.
• GitHub Repo

Software-Defined Radio Receiver Jan. 2025 - Apr. 2025

• Led a team of three to design, simulate, and manufacture the receive chain for a flexible radio transceiver.
• Designed the analog signal chain (8–16 MHz bandpass filter, ±0.7 V limiter, diode ring quadrature mixer, 96 kHz lowpass filter, 32 dB amplifier), verified it in LTspice against the interface control document, and validated the fabricated multilayer Altium PCB on the bench with PyVISA.

Custom RISC-V CPU Oct. 2024 - Dec. 2024

• Implemented a RISC-V-inspired CPU from scratch: register file, ALU, sign-extension unit, controller FSM, datapath muxing, and a memory controller over a 512x32 RAM.
• Designed the VGA display interface and the arbitration that lets the processor and the display adapter share one memory without contention.
• Built the ALU to cover addi, add, sub, xor, and, or, sw, lw, beq, and bne, verified against directed testbenches in ModelSim and synthesized in Quartus Prime Lite.
• GitHub Repo

Work-in-Progress: PiazzaPlus–Enhancing Piazza Search with Semantic Matching June 2026

Peer-Reviewed Conference Paper • First Author • ASEE Annual Conference & Exposition

• First author, co-authored with Professor Salma Emara.
• Presented at the ASEE Annual Conference & Exposition in Charlotte, North Carolina, the largest engineering education conference in North America, with over 4,000 participants.
• One of a small number of undergraduate presenters on a program dominated by faculty researchers.
• Covered the deployment and evaluation of hybrid semantic search in a live undergraduate course.
• View Paper

Languages: C++, C, Embedded C, Verilog, RISC-V Assembly, Python, Tcl, Bash

Hardware & Embedded: RTL design, logic synthesis, computer architecture, RISC-V, FPGAs, EDA, microcontrollers, STM32, memory-mapped I/O, interrupts, UART, SPI, I2C

Tools: Quartus Prime, ModelSim, OneSpin, Linux, Docker, Git, Flask, ChromaDB, OpenAI API, Jira, Confluence

Systems & Software: Data structures, algorithms, operating systems, concurrency, socket programming, large language models, information retrieval

Always open to discussing research or engineering opportunities. Email is the best way to reach me.

Email: ibraheem.elsheikha@mail.utoronto.ca

LinkedIn: Ibraheem El Sheikha